Fast Dynamic Power Consumption Estimation for DSP Systems

by Jonathan Clarke, George Constantinides, Department of Electrical and Electronic Engineering, Imperial College London, UK

The rapidly increasing power consumption of modern FPGAs demands that hardware designers pay careful attention to the power consumption of their designs to ensure acceptable battery life and/or junction temperatures. To do this it is essential to allow for the power consumption of a design to be estimated so that appropriate decisions can be made during the design process. The low-level power estimation tools provided by FPGA manufacturers can be prohibitively slow however (in the order of hours or days for large designs and long simulation vectors), and as such are also unsuitable to guide optimization for power consumption before or during synthesis.

This article summarises a tool being developed in the Department of Electrical and Electronic Engineering at Imperial College London for estimating the dynamic power consumed in arithmetic components on an FPGA. The tool allows for the dynamic power consumed by DSP algorithms, designed using the Synplify® DSP tool, to be estimated in a fraction of a second. This is achieved using statistical information about the internal word-level signals of the algorithm, acquired through high-level simulation, rather than through switching-level simulation as performed by tools available from FPGA manufacturers. Figure 1 shows an example system designed using the Synplify DSP tool, which allows functional blocks such as adders, multipliers, and delays to be easily configured and then connected together graphically.

Figure 1. A block diagram representing a 2-tap Least Mean Square adaptive filter using the Synplify DSP tool

The use of this tool allows power estimates to be made very quickly, and so could be used within the synthesis framework to optimize systems for power consumption, as well as to allow for fast power consumption estimates to be made during the design of a system.

Power consumption in digital circuits can be divided into static and dynamic power consumption, where static power consumption is due to leakage currents in the transistors of the circuit, and dynamic power is due to the capacitances inherent in CMOS circuits being switched between low and high voltage values. Whilst static power consumption is mostly determined by the size and number of transistors on a device, and can hence be estimated accurately by FPGA manufacturers, the dynamic power consumption of an FPGA can change significantly depending on the design which the device is configured to implement, and the signals which pass through it.

The power estimation tools provided by FPGA manufacturers use switching level simulations of placed and routed designs to estimate the dynamic power consumption in each component a circuit. Simulations of placed and routed designs allow for the average number of transitions each signal makes, and the capacitance it drives, to be estimated accurately, however these simulations can be extremely computationally intensive due to the number of logic gates and signals within a device.

The power estimation tool being developed is able to estimate the power consumed in blocks of logic such as multipliers or adders in a very short time, as power macro-models are used which have been characterised offline with training data acquired through extensive simulation of the individual blocks.

A power macro-model is an equation which estimates the power consumed in a particular component. The equation is built by selecting some measurable parameters of the input signals to the component, and using them as variables in the equation. These variables are weighted by coefficients whose values are determined through characterization using training data.

The macro-models in our work have been characterised using Gaussian input signals with varying values for their mean, standard deviation, and autocorrelation, as these parameters are known to strongly affect the switching activity in a signal [1, 2]. These signal parameters can be measured from a Simulink simulation of a system designed with Synplify DSP blocks, and are used in our macro-models to predict the power consumption in each block of the design.

To measure the power consumption in a system, our tool proceeds as follows. Firstly a Synplify DSP design is simulated in Simulink, using input signals as required by the system, which must be provided by the user. Each signal that connects Synplify DSP blocks in the system is monitored during the simulation, and the mean, standard deviation and autocorrelation for each signal is recorded when the simulation completes. Our tool then uses the appropriate macro-model for each Synplify DSP block in the system, along with the signal parameters measured for that block during simulation, to estimate each block’s power consumption. The total power consumed by the system is then estimated by summing the estimated power for each block. For a simulation of the system in Figure 1 lasting 1000 clock cycles, our tool can estimate the power consumption in 0.6 seconds. XPower, the low level power estimation tool provided by Xilinx, did not complete the power estimation process for a low level simulation using the same input data, due to a lack of disk space (over 40GB of storage was used by the program) after running for 22 hours.

The use of a macro-model incurs a cost in terms of the accuracy of the power consumption estimation made however. This is due to the use of word-level signal variables to predict power consumption, rather than performing a bit-level switching simulation of a system. Figure 2 shows graphs which compare the power estimates made by our tool for 12-bit and 16-bit multipliers, and for a 16-bit adder, against the estimates given by XPower. The mean relative error of the estimates made using this tool, compared to XPower, are 5% for adders and 7.2% for multipliers. This small loss in accuracy compares very favourably with the 99% increase in estimate speed possible with our tool.

Figure 2(a). Estimates of the power consumed in a 16-bit adder, compared with measurements from XPower.
Figure 2(b). Estimates of the power consumed in 12 and 16-bit multipliers, compared with measurements from XPower. In both figures the solid line represents the point of 0% estimate error, while the dashed lines represent error margins of ±10%

Work on the power estimation tool is currently continuing at Imperial College, with enhancements being developed which can quickly estimate the power consumed in components with unregistered (potentially glitchy) inputs, and to allow for the power consumption within the routing wires between components to be estimated. It is our aim to incorporate the power estimation tool into a pre/post-synthesis power optimization framework which would optimize, for example, the word-lengths of the components in a system, in order to minimize the system’s dynamic power consumption.

References:
[1] J. A. Clarke, A. A. Gaffar, and G. A. Constantinides. Parameterized logic power consumption models for FPGA-based arithmetic. In Field-Programmable Logic and applications, Tampere, Finland, 2005.
[2] J. A. Clarke, A. A. Gaffar, G. A. Constantinides, and P. Y. K. Cheung. Fast word-level power models for synthesis of FPGA-based arithmetic. In IEEE International Symposium on Circuits and Systems, Kos, Greece, 2006.