The Syndicated

Streamline Your IP Business with Higher Levels of Abstraction

Chris Eddington, Senior Technical Marketing Manager, Synplicity, Inc.

Whether you are involved in managing IP for internal organizational use or selling into commercial markets, you are familiar with the challenges of scaling your operations to include broader sets of users and faster, easier reuse. Synthesizable Verilog/VHDL cores often require a lot of hand holding and almost always have “hard coded” functionality and optimizations that limit the applicability or ease of use. There are tradeoffs involved in how much effort goes into making them more flexible and portable versus development costs and time to market. Even so, cores usually require significant hand tuning when using them on new technologies or devices for which they were not originally developed.

Furthermore, IP with DSP functionality poses yet another set of challenges. The arithmetic nature of DSP algorithms creates architectural tradeoffs that are very dependent on the target technology. This usually involves choosing a degree of parallelization in the implementation of the digital arithmetic such as multipliers or additions. These architectural choices have significant impact on the speed and area of the implementation for a given FPGA or ASIC technology.

Synplicity^® believes a comprehensive approach to this problem is to provide a high level DSP modeling environment that provides both hardware and architectural abstraction along with a DSP synthesis engine that automates creation of optimal architectures and mappings to hardware resources. With such an approach, engineers can focus on capturing algorithm behavior and eliminate the coding and verification of architectural optimizations and hardware-specific features. The DSP synthesis engine then allows the designer to create different architectures, from fully parallel or more serialized, to explore speed and area tradeoffs. The net result is significantly faster development and portability of IP.

This DSP synthesis methodology is the unique approach used in Synplicity’s Synplify^® DSP product. It enables engineering teams to create technology-independent and easily extensible IP models that are fully optimizable to most FPGA and ASIC technologies. As shown in Figure 1, the core advantage of IP created in the Synplify DSP tool is that it can automatically generate many possible points on the area/speed (or serial/parallel) tradeoff curve. From a single model, engineers can create a parallel implementation or more serialized implementation that uses less area. The optimizations take into account the timing and capacity of the target device, so models can be automatically retargeted to different technologies using an optimal architecture. This enables significantly higher productivity for IP used across multiple implementations, perhaps initially in an FPGA which is radiation hardened then implemented into a lower cost FPGA or ASIC.

Figure 1. Synplify DSP enables speed/area exploration from a single model

To enable ease of use and full hardware and architectural abstraction, the Synplify DSP tool provides its own blockset in Simulink which contains built-in support for many commonly used DSP functions, plus the facility for users to extend this blockset for their own internal DSP IP, or for functions not yet supported by the Synplify DSP software. The result is a blockset that is both technology independent and user extensible, and can be used directly within Simulink for design space exploration.

Today there are over 80 different functions in the Synplify DSP blockset, with dedicated libraries for the following areas:

Communications
Control Logic
CORDIC
Filtering
Math Functions
Memories
Ports and Subsystems
Signal Operations
Sources
Transforms

Adding custom functions to this blockset is straightforward and a tutorial for this is included in the Synplify DSP tool. Once a custom library is developed, it can automatically become synchronized with later versions of the software. An additional productivity advantage is that new customized blocks can be built using existing library functions as primitives, giving users the flexibility to create special-purpose libraries that are specially tuned versions of the existing Synplify DSP blockset or their own custom blockset.

The core set of functions provided in the Synplify DSP blockset continues to grow, with higher complexity functions now being added. A recent addition to the communications blockset is a Viterbi decoder which decodes convolutionally encoded input data and outputs single-bit decoded data. It implements a fully parallel ACS (add-compare-select) operation, suitable for high speed applications. As part of the Synplify DSP blockset, it can be easily instantiated into the overall design, and various parameters (shown in Figure 2) can be defined using the graphical UI.

Figure 2. Viterbi decoder model parameters

The Viterbi decoder provides a good example of the power of a technology-independent blockset instead of handcrafting the RTL code for it. In RTL, a core like this has to be handcrafted and manually optimized (typically taking weeks) and there are a number of architectural tradeoffs to choose. Once implemented, any design migration to another FPGA platform (or ASIC) would take additional weeks of manual effort. By comparison, the Synplify DSP technology-independent and architecturally independent approach allows designs using the Viterbi decoder to be automatically pipelined or serialized based on the user’s optimization choices. These optimizations are done after the model behavior is created and verified within Simulink. Operations within the block, such as memory and multipliers, will also be automatically described in a way that will map to the appropriate resources in the target technology.

Summary

In summary, Synplify DSP’s methodology and modeling library is unique in providing automation for IP development, optimization, and design migration. Achieving optimal quality of results is facilitated by architectural abstraction and a powerful synthesis engine that can automatically optimize the architecture based on the target technology. These powerful capabilities make Synplify DSP the best possible way to rapidly scale your IP business.