Tips & Hints

Synplify Premier and Synplify Pro Software

Q. Can you run a Synplify Premier or Synplify Pro flow on a Xilinx EDK project ?

A. Yes. Xilinx Embedded Development Kit (EDK) is used for designing embedded processor systems and subsystems in Xilinx FPGAs with embedded IBM PowerPC™ hard processor cores and/or Xilinx MicroBlaze™ soft processor cores.

EDK generates the hardware platform in HDL format and then runs XST to synthesize each core into a separate NGC file. At the end of this, the platform is imported into the Synplify Pro/Premier tool using a utility called edk2syn, and then synthesized and implemented as a regular hardware design along with the user’s custom logic (if any).

The edk2syn utility converts an EDK project file (XMP) to a Synplify project file (PRJ). The resultant PRJ file can then be opened in Synplify Pro/Premier. Synthesis and Place & Route can then be run with the push of ‘Run’ button to produce a bitmap file. This bitmap can then be imported back to EDK with one click to create a download file.

Here is a step by step guide for running Synplify on an EDK design/system

Generating a Synplify Project

1. Create the EDK project using XPS GUI and change the following settings:

Project->Project Options->Hierarchy and Flow:

Select Implement design in ISE (Export to Project Navigator Flow: DEPRACATED)

2. Run the project using Hardware->Generate Netlist

3. Import EDK project into Synplify Pro/Premier

4. Open command shell and run:

edk2syn –xmp <XMP file>

Example: edk2syn -xmp E:/EDK/basic_ppc/system.xmp

For more details on options, see command line help by running: edk2syn –help

Running Synplify Pro/Premier

1. Open synplify/synplify.prj file using Synplify Pro/Premier.

2. Click the “Run” button in Synplify to synthesize and Place & Route the embedded hardware system

Importing the Bitmap File Back Into XPS

1. Go back to the XPS GUI and select Project ->Import from Project Navigator.

2. Then Select the BIT file and BMM file from PAR directory as shown

BIT File = synplify/rev_1/par_1/system.bit

BMM File = synplify/rev_1/par_1/system_bd.bmm

3. Click OK

4. Run : Device Configuration->Update Bitstream

Bitstream is ready for download into the FPGA.

Q. Can you change parameters in the project file while running in batch mode?

A. Yes.

To set parameters in batch mode:

1. Declare the variable you want in project file with the following syntax:

C-shell users:

setenv <variable_name> <value>

For example: setenv freq 210

K-shell/Bash shell users:

export <variable_name>=<value>

For example: export freq =210

2. Use these variables in the project file as $env(variable_name).

Example

If you want to change the frequency from one run to another, declare the following the lines in the project file:

set_option –frequency $env(freq)

and declare the same variable as

setenv freq 210 ( In c-shell)

export freq=210 (In K-shell or bash shell)

Run the project in batch mode using synplify_pro –batch <project_name>.prj

The frequency will now be 210 MHz.

You can simply change the frequency in the command prompt by defining the variable as shown above to a new different value. A subsequent run will take the new frequency.

Q. Can you use Xilinx IP Cores in the Synplify Premier and Synplify Pro tool flow?

A. Yes. Xilinx IP Cores are available in three formats – EDN, NGC and NGO. While EDNs are in EDIF format, NGO and NGCs are in binary file formats.

The Synplify Pro and Synplify Premier tools can read the contents of unencrypted EDNs to extract timing information to be used during synthesis. The EDN cores will be used only for timing analysis and will not be subjected to any other synthesis optimizations.

While the Synplify Pro and Synplify Premier software can read EDN cores, they cannot read the NGC/NGO cores directly. These formats first need to be translated to EDIF format by executing the Xilinx utility: ngc2edif. Once this is complete, they may be included in the Synplify Pro or Synplify Premier project. Irrespective of whether the cores can be read by the Synplify Pro/Synplify Premier tool, they need to be made available to Xilinx ISE along with the EDIF netlist produced by the Synplify Pro/Synplify Premier software for P&R.

In addition, the Synplify Premier tool can read the NGC/NGOs by internally calling the Xilinx utility ngc2edif and converting the NGC to EDIF format automatically during physical synthesis (provided the cores are added to the project and Physical Synthesis is enabled). The translated core will have the default extension .NDF.

Also, both EDN cores and NGC/NGO cores are absorbed into the final netlist produced by Synplify Premier and therefore they need not be included separately during P&R. The Synplify Premier software uses these cores during physical synthesis for both timing information and optimizations. However, if the IP cores are SECURE, the secured (encrypted) cores are NOT absorbed into the final netlist or the physical synthesis database. Such cores will be used only to obtain timing information.

Determining whether a Xilinx IP Core is secure

After translating the NGC/NGO core to EDIF (.ndf) by using the Xilinx Utility ngc2edif, if the translated core (.NDF file) has INIT values for all the LUTs, then it is a non-secure core. If the LUT configuration does not contain INIT values, the NGC/NGO is SECURED.

Certify Software

Q. Can a user specify board trace delays in the Certify tool?

A. Yes, the user can currently specify a timing delay between a logical path (net) for instances that crosses between two devices via the define_route_delay attribute. Essentially, this is adding an extra timing component to a logical path that will be further taken into consideration during the timing optimizations in the synthesis run. The requirement is for user to either approximate this trace delay or get the information from the board vendor on that board trace delay. The attribute is used to add the delay to logical paths and not physical traces and the user will have to add this manually to all logical paths that he desires to constrain between the FPGAs.