The following is an excerpt from a recently published white paper. Click the link at the bottom of the excerpt to read the entire paper.

Infusing Speed and Visibility into ASIC Verification-100% internal signal visibility for FPGA-based ASIC/SoC prototypes and FPGA-based systems running at real-time hardware speeds!

By Mario Larouche, Engineering Director, Synplicity, Inc.

Introduction

High-performance, high-capacity FPGAs continue to experience an exponential growth in usage, both in their role as prototypes for ASIC/SoC designs and as systems in their own right. These designs typically involve complex combinations of hardware and embedded software (and also, possibly, application software). This is resulting in a verification crisis, because detecting, isolating, debugging, and correcting bugs now consumes significantly more time, money, and engineering resources than creating the design in the first place.

The problem is that bugs in this class of design can be buried deep in the system and they may manifest themselves in non-deterministic ways based on complex and unexpected interactions between the hardware and the software. Simply detecting these bugs can require extremely long and time-consuming test sequences. Once a problem is detected, actually debugging the design requires a significant amount of time and effort. Furthermore, when verification tests are performed using real-world data such as a live video stream from a digital camera, an intermittent bug may be difficult (if not impossible) to replicate.

There are a variety of verification options available to engineers, including software simulation, hardware simulation acceleration, hardware emulation, and FPGA-based prototypes. Each approach has its advantages and disadvantages (Table 1). RTL simulators, for example, are relatively inexpensive, but full-system verification performed using this approach is extremely slow. One major advantage of software simulation is visibility into the design. Having said this, as more signals are monitored and the values of these signals are captured, the simulation slows still farther.

Table 1. Comparison of conventional verification technologies

At the other end of the performance curve are FPGAs, which offer a significant advantage with regard to their ability to run at real-time hardware speeds. In the case of ASIC/SoC designs, FPGA-based prototypes are also relatively inexpensive as compared to hardware acceleration and emulation solutions. Until now, however, FPGAs have suffered from the problem of gaining visibility to their internal state and signals.

This paper first provides an overview of the various conventional verification options available to designers and summarizes the advantages and disadvantages of these different techniques. The paper next introduces an innovative, patented new technology called TotalRecall™, which provides 100% visibility into an FPGA - including the registers, combinational logic, and memory blocks - while allowing the FPGA to be used at full real-time hardware speeds. When a bug is detected, the data from the TotalRecall technology can be used to initialize a software simulator with the state of the design hundreds or thousands of cycles before the bug occurred, and also to provide the test sequence that will take the design from this initial state to the bug.

To read the entire white paper, click here.