The Syndicated

How to Use the Synplify Pro Tool Version 8.8.1 with the New ISE 9.1i SmartCompile Incremental Flows

By Frederic Rivoallon, Sr. Manager; Software Product Mktg., Xilinx Corporation

Xilinx® ISE software introduced new SmartCompile incremental design flows in its 9.1i release. SmartCompile includes two different technologies, SmartGuide and Partitions, each with a corresponding flow. This document explains how to use these flows with the Synplify Pro® tool.

SmartGuide

SmartGuide minimizes changes in a design implementation compared with a previous implementation that is used as a reference. Typically, the user synthesizes the design to get an output netlist, which ISE places and routes. The user then makes a change to the RTL, reruns synthesis and then reruns ISE P&R with SmartGuide enabled.

If the user selects to use SmartGuide, P&R attempts to do the minimal place and route changes based on what's changed in the netlist, while still maintaining a legal netlist and still meeting timing.

The benefits of SmartGuide are twofold: design preservation and runtime reduction. SmartGuide uses a name-based algorithm and recognizes identical instances in both implementations. LUTs, flip-flops, DSP blocks, etc., are preserved as much as possible, including routing nets. Matching these elements saves time during the packing of the logic into slices, during placement, and also during routing. On average, the P&R runtime reduction is halved and most placement and routing is preserved. This runtime reduction will be more apparent for designs with P&R runtimes of one hour or more.

SmartGuide will work best if the RTL changes are applied to a design already meeting timing and if these new changes do not cause a timing constraint to fail.

Fig 1: Layout of a design after SmartGuide is applied

Here is a list of DOs and DON’Ts for SmartGuide:

Table 1: DO’s and DON’Ts with SmartGuide

SmartGuide does not require any special settings in synthesis. To make it work, synthesis needs to preserve most names from one synthesis run to the next after a change to the RTL. Synplify Pro software meets this requirement very efficiently and preserves a maximum number of names from one synthesis run to the next after a small change is made to the RTL.

How do we define a “small” change? SmartGuide will work best if the change is small at the netlist level (no more than 10% new or modified logic). In the RTL code, most small changes will result in small changes at the netlist level. For example, changing the logic condition on a “if” statement, making a modification to the state transitions of a state machine, or changing a design revision constant register will generally result in a limited amount of changes in the netlist. Some other limited RTL changes can have more impact on the netlist, for example constants that are pushed throughout the design can yield vast changes. Changing a loop index on generate statements can also result in many changes. These changes, although “small,” are likely to have a big impact to the resulting netlist, and lower SmartGuide effectiveness.

It is also recommended to replace the reference design after 10 to 15 consecutive design changes; otherwise the guide (the result of the first synthesis and ISE run) will be too different compared to the current version of the design and the runtime savings might be lost because there are so many incremental changes to make.

Finally, note that ISE provides a summary of the SmartGuide compile in the MAP and PAR report, and also generates a specific guide report file (.grf) with general statistics and change details.

Partitions

Partitions constitute an incremental block based design flow – It allows incremental ISE P&R to run on a module by module based on RTL hierarchies. The ISE 9.1i Partition flow offers exact preservation of blocks down to the routing, and allows you to isolate unchanged portions (blocks) of your design from the portions of the design that you wish to modify.

The benefits of Partitions are exact preservation of blocks, and runtime reduction.

Partitions are first set on hierarchical blocks by tagging them as compile points. The next step after synthesis is to read the EDIF netlist into the ISE environment. Xilinx software will read timestamps in the EDIF and recognize the compile points as partitions. During the first implementation of the design (step #2 in graph below), ISE builds a Partition database . Both the Synplify Pro tool and ISE will evaluate changes applied to the design and determine if a compile point (or Partition) needs to be re-implemented or not.

Fig 2: Partition flow in ISE.

Partitions require that each logical module or entity be synthesized by itself. This is accomplished by using the MultiPoint™ flow in the Synplify Pro software. This flow isolates each RTL logical module marked as a compile point.

With Partitions, users can choose the level of preservation: Partitions have a customizable level of preservation, with 4 values: “synthesis” (preserve the netlist), “placement” (preserve the netlist and placement), “routing,” (preserve netlist, placement and routing) and “inherit” (use in sub-blocks only when you want the preservation level of the sub-block to be the same as that of its parent block). The default setting is “routing”; for which the synthesis netlist, placement, and the routing will all be exactly preserved from one run to the next (provided the RTL within the compile point block was unchanged).

In a first step, in the Synplify Pro tool, specify compile points (which ISE will automatically interpret as Partitions): To set a compile point and ensure that ISE recognizes it as a Partition, mark the compile point with a type “locked, partition” (prior to 8.8.1 it was “locked, physical”). Here is an example:

You can specify your compile points in the GUI using the SCOPE editor or via the Synplify Pro command line.

Synplify Pro software generates a timestamp for each partition. At the end of synthesis, the Synplify Pro tool will insert a timestamp– a number associated with the Partition -- into the EDIF netlist for each partition. Here is an example

This timestamp will only change in subsequent netlists if the contents of the partition (compile point) are re-synthesized.

The next step is to read the netlist into ISE. Once read into Project Navigator environment, ISE recognizes the Partitions automatically:

Fig 3: Partition information in Project Navigator

Right click on a Partition to get access to a Partition Properties menu item. At that point you will be able to change the default level of preservation for example, from “routing” to “placement” if needed.

For a command line based flow, TCL is required. If a netlist has Partition timestamps and is implemented with the command line without TCL, then the partition will be ignored. For more information on TCL, please read the Xilinx development reference guide (http://www.xilinx.com/support/sw_manuals/xilinx9/download/dev.zip). Chapter 3 is devoted to TCL.

Here are some DOs and DON’Ts tips when using the Partition flow:

Table 2: DO’s and DON’Ts with the Partition flow

Conclusion

Synplify Pro software can take advantage of SmartCompile. The SmartGuide flow is transparent to the Synplify Pro user and works automatically. Partitions leverage the Synplify Pro MultiPoint flow which will insert timestamps in the netlists so that ISE knows which blocks have been modified from one synthesis run to the next and thus which blocks to run incremental P&R on. ISE will then read the Partitions from the netlist in the Project Navigator GUI or with TCL for a command line compile.

The SmartGuide and Partition flows allow you to save significant design runtime and preserve portions of your design from one design iteration to the next.