Field Programmable SoCs Require IP-centric Solutions

Editor's note: Angela Sutton, Sr. Product Marketing Manager for FPGA Implementation Products, is guest writing this article for Ken McElvain.

A recent survey conducted anonymously by Synplicity to FPGA designers revealed wide scale use of system level components and Intellectual Property cores (IP).  Over 40% of designs from those surveyed included an embedded microprocessor and additionally, over 30% of designs deployed some other form of non-processor IP. 

FPGAs are appealing to ASIC designers -- Some are for the first time choosing to implement the next generation of their product in an FPGA instead of an ASIC. Others are choosing to first verify their ASIC design by implementing the hardware for their system in an on-board FPGA.  These designers require the very IP that they used or plan to use on their ASIC now be available on an FPGA.

The benefits of IP availability to FPGA designers are many:  The ASIC designer can re-use their system software investment from the ASIC if they are now migrating to an FPGA;   If new software development or hardware/software tuning is required for the eventual ASIC, designers can get a head start on system software development and test using an FPGA prototype board to mimic the ASIC.

It’s therefore no surprise that 3rd party IP including processors, peripherals, bus interfaces, DSP and telecommunications cores, previously only seen in ASICs, are now becoming readily available for FPGAs.  At the same time, several FPGA providers offer proprietary microprocessors, peripherals, and IP core generators to their customers.

For the 3rd party IP provider who wishes to deploy their IP to the broad FPGA customer base, there is a need to provide functioning IP that can be fully integrated, optimized, and verified in the context of an FPGA system.  The IP provider’s crown jewels -- their Intellectual property, particularly in the form of RTL -- need to be usable but protected.  For this reason, Synplicity donated an open IP standard that is now undergoing a standardization effort in the IEEE.  The RTL can be secured by the IP provider using this standard, yet it is synthesizable and verifiable.  Using this scheme, timing and resource information for your entire FPGA system design is available early, immediately after synthesis, allowing you to assess system-level performance.  

For consumers of FPGA vendor proprietary cores, there is a similar need for timing and resource-accurate design flows – Synthesis tools must fully integrate with the source of the FPGA vendor cores, whether they originate from the vendor’s own core generators, whether or not the vendor has encrypted it, and whether or not it is presented at a system level as the output from one of the vendor’s design kits such as Xilinx’s Embedded Design Kit (EDK) and SystemGenerator tools, or Altera’s SoPC Builder and DSP Builder tools.

For many designers who have integrated these cores, it remains a priority to verify the design “at speed” on a hardware platform. For example, a video chip designer can better debug and improve their design if they can view video that refreshes at close to the normal video frame rates.  Fortunately solutions such as the Confirma verification platform have emerged to meet this need.  These platforms are built upon FPGA boards that have been performance optimized -- you may either implement your design including IP cores in the on-board HAPS FPGAs, or attach a 3rd party IP provider’s daughter card, such as an ARM processor card, to the HAPS board directly.

FPGA designs are rapidly approaching ASIC complexities and demand a new generation of IP-centric solutions that make System designers as productive as possible.