Automatic IP Micro-Architectural Optimization in Synplify DSP

By Chris Eddington, Director of DSP Marketing, Synplicity, Inc.

Synplicity’s Synplify® DSP software has achieved a large number of mission critical product deliveries for algorithmic signal processing applications where portability and key IP (intellectual property) cores have played a significant role to reduce time-to-market and also improve reliability throughout the design cycle. The Synplify DSP tool uses an industry-leading DSP architectural synthesis methodology that delivers the ultimate modeling abstraction and optimized portability across all major FPGA and ASIC technologies.

Micro-Architectural Optimizations Defined

The Synplify DSP blockset provides critical application-focused IP such as filters, FFTs, error correction, and CORDIC math functions that speed the model creation process. Synplicity builds into these cores the ability to select an optimal “micro-architecture” when they are implemented so that they achieve optimal area for the given target technology, sample rates, precision, and user optimization constraints. This is a fundamental capability that makes portability effective across a wide range of FPGA and ASIC technologies. The Synplify DSP development team is constantly adding and improving the cores to accommodate new techniques and target technologies.

Micro-Architecture Examples

FIgure 1

Figure 1 illustrates how micro-architectural optimization works for an FFT block embedded in a larger model. In the usual Synplify DSP flow, the user provides constraints to define what kind of system-wide architecture is desired. When the Synplify DSP synthesis engine reaches an IP block, it inherits the sample rate and precision from the way it is instantiated in the design. Based on this information, the synthesis engine explores how different micro-architectures implement on the target technology and chooses the one which meets timing constraints and achieves the lowest area. For example, a linear-interpolated lookup table (LIL) approach might be used versus an iterative multi-cycle algorithm. Other options might include how much pipelining is used and different coding styles for memories and shift registers. In the figure, a user’s single algorithm model can result in a highly pipelined FFT using 12 multiplier blocks, or a highly serialized micro-architecture using just one multiplier and more Block RAM, or a range in between these. To maintain a reliable verification flow, the different micro-architectures are synthesized with the appropriate precision and control logic to remain bit and cycle accurate with the model behavior.

The FIR core is another important example where many different optimization techniques are explored to achieve best results. The FIR micro-architectural exploration includes:

• Transposed or Direct Form architecture
• Coefficient reduction for symmetric, anti-symmetric, repeated, or trivial values
• Minimal pipeline stages to meet timing
• Serialized, multiply sharing for better area
• Inferring full speed hardware multiplier-accumulator structures when needed

For a single model using a 16-tap symmetric FIR filter, examples of this automatic exploration and tuning process can result in:

• Fully parallel structure using 16 hardware multipliers if sample rate is close to device FMAX
• Coefficient sharing structure using 8 hardware multipliers if sample rate constraints are loose enough
• Transposed architecture with coefficient optimizations when targeting ASIC (which usually yields best area for a given sample rate)

Many other Synplify DSP functions include automatic micro-architectural optimization as shown in Figure 2. For example, all the CORDIC functions can select between stages of high-speed pipelined implementations versus a lower area, iterative approach.

Figure 2

Effective Methodology

Synplicity believes IP micro-architectural synthesis is a fundamental and critical requirement for an effective Electronic System-Level (ESL) design solution and will continue to improve and expand the IP portfolio in the Synplify DSP software. This is especially true for high-level models to be truly portable and optimized across FPGA and ASIC technologies. The net result is significantly faster development and portability of IP for FPGA products, ASIC prototyping, and ASIC development.

To learn more about the Synplify DSP software, visit http://www.synplicity.com/products/dsp_solutions.html.