Xilinx Core Flows In The Synplify Pro^® and Synplify^® Premier Software

By Angela Sutton, Sr. Product Marketing Manager for FPGA Implementation products, and Chuck Banken, Senior Field Applications Engineer, Synplicity, Inc.

A survey by Synplicity showed that about 40% of designers use some sort of Xilinx generated core in their design.  While some of these cores are relatively small, others are more complex and several, including the Xilinx MicroBlaze microprocessor, are delivered in an encrypted form. 

Prior to Synplify Pro and Synplify Premier v9.0.2, Synplify was unable see inside Xilinx encrypted cores.  Moreover, Synplify Pro users frequently merged secure and non-secure cores into the design after they had run synthesis, missing many opportunities to improve results during synthesis.    Now Synplify’s internal optimization engine can read and completely incorporate all of these cores in your design.  Even secure Xilinx cores are directly merged into your design during synthesis, where they now can be accurately timed.  These cores can also, be optimized by Synplify Premier. As a result, you will see better timing estimates in your Synplify Pro and Synplify Premier timing report and these tools also benefit from this better visibility inside the cores when it performs optimizations, leading to better quality of results.  

You will no longer have to manually floorplan .ngo cores, such as RAMs, if you use the Synplify Premier tool.  Previously, .ngo cores had to be floorplanned before you could run place and route in any Synplify Pro flow, or before you ran Synplify Premier’s Graph Based Physical Synthesis. Synplify Premier now optimizes and places the entire design automatically without any requirement for floorplanning these cores, providing you with improved automation.

Including Xilinx IP in your design

Beginning with the 9.0.2 release, Synplify Pro and Synplify Premier software can read Xilinx IP cores in the following formats:

• EDN (EDIF netlist)
• NGO (Xilinx netlist)
• Non-secure NGC (Xilinx netlist)
• Secure NGC (Xilinx encrypted netlist). 

Before 9.0.2, only the EDN (EDIF netlist) and non-secure NGC (Xilinx netlist) formats were supported.

To synthesize a design that includes any of these cores:

1. Instantiate the Xilinx cores in your RTL and include the appropriate EDN, NGO and/or NGC cores (files) in your Synplify Premier or Synplify Pro project.  Figure 1 shows an example
2. Run synthesis. The output netlist files (and constraint files) are copied automatically to the place and route directory if you choose to run ISE from the Synplify Pro or Synplify Premier software.
3. To maintain security, Synplify Pro and Synplify Premier software re-encrypts secure cores before they are passed to the ISE Place and Route tools.  You will only be able to see inside the non-secure cores when you debug your design using HDL Analyst.

Figure1: Include your instantiated cores in your Synplify Pro or Synplify Premier design project

Xilinx IP in a Logic Synthesis (Synplify Pro) Flow

If Xilinx IP is included in the synthesis project file, the Synplify Pro tool uses the IP in synthesis to 1) extract timing & resource usage information for the IP, and 2) absorb the core into the output netlist generated.  Unlike Synplify Premier, Synplify Pro software does not optimize or modify the IP netlist.  It is recommended that logic synthesis read the Xilinx cores, but not required.  If synthesis reads the Xilinx IP, it will always extract timing & resource information from it. The Synplify Pro tool will generate a main netlist for the design, including all unencrypted cores. Separate encrypted edif files are generated for each instantiation of  encrypted core. and these encrypted files referenced by the main output edif file generated by the Synplify Pro tool. Be sure to include all of these Edif files in your Place and Route directory before running place and route.

Including the IP in your Synplify project and Synplify design allows synthesis to infer the timing of the IP and to optimize the surrounding logic that interfaces with the IP. The Synplify Pro software also includes the IP in its output automatically. If you have cores that you have not included in the Synplify project, the Synplify tool issues a warning such as:

@W: MT246 |Blackbox port_fifo_ram is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results).

Why specifically will including cores in your design help you to get better results in the Synplify Pro software? Without the IP included in the design, logic synthesis would assume that the IP has ideal timing characteristics and would allocate all of the timing budget to the surrounding logic. Note that you can specify the timing characteristics of a blackbox using attributes and directives such as syn_tco for the blackbox. Clearly, having synthesis read the IP core and extract the timing information should be much easier than having to manually determine the timing of the blackbox and specify it with attributes.

When synthesis reads the Xilinx IP cores, the resource usage data in the synthesis log file reflects the resources consumed by the core. Also, knowing what’s in the IP core may influence how synthesis performs resource allocation for the remainder of the design. For example, if the IP cores contain many DSP blocks, synthesis may use this knowledge to implement more of the remaining design’s multipliers in discrete logic, so as not to exceed the maximum number of DSP blocks available in the FPGA.

Xilinx IP in a Synplify Premier Graph Based Physical synthesis Flow

It is required that Synplify Premier’s physical synthesis read the Xilinx IP cores.  Physical synthesis by default uses the Xilinx IP cores that you included in your Synplify project to 1) extract timing and resource information & 2) optimize the IP netlist. Why would you want to have synthesis optimize a Xilinx IP core? The IP core is designed without full knowledge of the context in which it will be used.  For example, it is possible that an output of an IP core might be instantiated into a design where it drives hundreds of user loads and becomes timing critical.  Allowing synthesis to replicate the source inside the IP core could easily fix this timing problem.  Also, a common design technique, even for IP cores, is to create a general solution with everything that would ever be required and have downstream tools prune away unnecessary logic depending upon design context and which outputs of the IP are used.  If this pruning is disabled in synthesis, then the synthesis log files may over-state resource usage, as the pruning will only occur later within ISE.

Physical synthesis also uses the IP core to obtain placement information.  This bears a little more explanation. Synplify Premier’s Graph Based Physical Synthesis simultaneously performs placement and logic synthesis.  Like Synplify Pro, Synplify Premier generates a netlist but it additionally creates an optimized and legalized placement and placement constraints and it forwards this information to ISE where final routing will be performed.   For this to work, all Xilinx IP must be included in the design project so that a complete placement can be generated by Synplify Premier and physical synthesis can correctly place other logic with respect to the IP core.   The table below explains exactly what happens in Synplify Premier.

Table 2: How Xilinx Cores are handled by the Synplify Premier software

Using The Synplify Pro and Synplify Premier Tools With EDK Cores

Synplify Pro and Synplify Premier have been integrated with the Xilinx Embedded design kit (EDK) flow.  EDK generated cores can be included in your design using the secure and non-secure NGC flows.   If you use the Microblaze Microprocessor soft processor from Xilinx, you can incorporate it in your design using the secure ngc flow.  For more details, about this and the underlying EDK2SYN script, please feel free to contact Synplicity customer support or the Technical Resource Center website accessible by the software.