The Syndicated

Tips & Hints

Synplify Premier Software

Q. Can you use the Synplify Premier Design Planner for IO placement?

A. Yes. Assigning logical ports to physical pins is facilitated by the interaction of the Design Planner and the RTL View.

The following steps can be used for this purpose. Notice that only usable IO pins are displayed In the Design Plan:

Enable EXPANDED PIN VIEW by selecting: View->Expanded Pin View.

2. Adjust the pin view to modify pin size by selecting: View->Adjust Pin View.

3. Drag & Drop ports to pin locations. To assign ports, do one of the following:

Assign from the RTL View or from the Hierarchical Browser.
Assign a port to a pin location in any Design Planner view.

Since there are other methods of assigning I/O pins, the following is an example of a pin assignment conflict you might encounter:

The .sdc file might contain I/O pin locks that conflict with the pin locks specified in the .sfp file. The SCOPE constraint file (.sdc) takes precedence over the Design Plan file (.sfp) when conflicts exist after pin assignments. It is highly recommended that you avoid creating mismatches in the .sdc and .sfp files by choosing only one format.

Synplify Pro Software

Q. Can you use the 64-bit version of Quartus with Synplify Pro on a 64-bit UNIX platform?

A. Yes. To use the 64 bit version of Quartus with Synplify Pro on a 64 bit UNIX platform, set the environment variable “QUARTUS_64BIT” TO 1

For example:

.bashrc => export QUARTUS_64BIT=1
.cshrc=> setenv QUARTUS_64BIT 1

Now the Quartus used by Synplify Pro in all of the following combinations will be 64-bit version Quartus.

Menu Options->QuartusII->Launch Quartus
Menu Options->QuartusII->Run Background Compile
Run Place & Route from P&R implementation.

To confirm that Quartus is being run in 64 bit mode, you can observe the following line in the .rpt files (ex <design>.fit.rpt, <design>.map.rpt, etc)
“Quartus II 64-Bit Version 7.2 Build 151 09/26/2007 SJ Full Version”
Note: Using 64-bit versions of Quartus II executables allows you to access more than 4 GB of memory per process and facilitating designs that require large amounts of memory to compile.

However, compiling designs with 64-bit versions of Quartus II executables can require 50-100% more memory than the same design compiled with 32-bit versions. For example, if your design requires more than 3 GB of memory with the 32-bit version, you should have at least 6 GB of memory installed for a 64-bit compilation.

Q. Does Synplify Pro Software Infer EBRs For Lattice Devices?

A. Yes. Starting from Synplify Pro version 8.8.1, the tool infers Lattice Embedded Block Rams (18KB memories with input and output registers) from your RTL code.

EBRs can be implemented as Single Port, Dual Port, or Pseudo Dual Port memories.

EBRs are initialized with a $readmemb/h in the code, which gets translated to INITVAL_00=320'h070601C7980F1921876E06018070F000AC000A800……….” format in verilog simulation netlist file.

EBR memory supports three forms of write behavior for single port or dual port operation:

Normal – Data on the output appears only during a read cycle. During a write cycle, the data (at the current address) does not appear on the output. This mode is supported for all data widths.
Write Through – A copy of the input data appears at the output of the same port during a write cycle. This mode is supported for all data widths.
Read-Before-Write – When new data is being written, the old content of the address appears at the output.This mode is supported for x9, x18 and x36 data widths.

Example 1 (Single port ram in “NORMAL” mode):

module test02 (clk,we,addr,data_in,data_out);

parameter addr_width = 10;
parameter data_width = 18;

input clk,we;
input [addr_width - 1 : 0] addr;
input [data_width - 1 : 0] data_in;

output [data_width - 1 : 0] data_out;

reg [data_width - 1 : 0] data_out;
reg [data_width - 1 : 0] mem [(2**addr_width) - 1 : 0];

always @ (posedge clk)
begin
if(we) mem[addr] <= data_in;
end

always @ (posedge clk)
if(~we) data_out <= mem[addr];

endmodule

Example 2 (Single port ram in “Read Before Write” mode):

module test04(clk,we,addr,data_in,data_out);

parameter addr_width = 10;
parameter data_width = 18;

input clk,we;
input [addr_width - 1 : 0] addr;
input [data_width - 1 : 0] data_in;

output [data_width - 1 : 0] data_out;

reg [data_width - 1 : 0] data_out;
reg [data_width - 1 : 0] mem [(2**addr_width) - 1 : 0];

always @ (posedge clk)
begin
if(we) mem[addr] <= data_in;
end

always @ (posedge clk)
data_out <= mem[addr];
endmodule

Example 3 (Single port ram in “Write Through” mode):

module test05 (clk,we,addr,data_in,data_out);

parameter addr_width = 10;
parameter data_width = 18;

input clk,we;
input [addr_width - 1 : 0] addr;
input [data_width - 1 : 0] data_in;

output [data_width - 1 : 0] data_out;

reg [addr_width - 1 : 0] addr_reg;
reg [data_width - 1 : 0] mem [(2**addr_width) - 1 : 0];

always @ (posedge clk)
begin
addr_reg <= addr;
if(we) mem[addr] <= data_in;
end

assign data_out = mem[addr_reg];

endmodule