The Syndicated

ASIC Verification In Transition – How To Get The Most Out Of FPGA Prototyping!

By Juergen Jaeger Senior Director, ASIC Verification Marketing, Synplicity, Inc.

ASIC, ASSP and SoC development is and will always be a risky and expensive business. Add to this the fact that functional verification makes up 50% to 70% of the development effort today and it becomes obvious that traditional verification methodologies alone are not sufficient any more to keep up with growing design complexities and shrinking design cycles.

The unparalleled verification performance coupled with the ability to act as a software development platform makes prototyping one of the fastest growing verification methodologies today. And although virtually every ASIC, ASSP and SoC that is developed today is prototyped on an FPGA board, many still consider prototyping an ad-hoc methodology – and not a mature verification solution. This perception has some validity to it, because there is still a lot of “assembly required” to make a custom prototype board work successfully. However, only prototyping offers the performance, flexibility, and capabilities that are necessary to master some of the most critical verification challenges facing designers today. As a result, FPGA prototyping is quickly evolving – growing up – to address these challenges. FPGA prototyping is turning into a highly productive, easy to use verification methodology.
Most development teams employing a hardware-based approach today design the prototype board in-house, but with mounting chip complexity, prototype board development itself becomes a tough problem that demands unique expertise. With multiple million-gate FPGAs on board, pin counts in the thousands, and 20+ board layers to manage, a new level of sophistication is needed to craft a prototype board.

Off-the-shelf FPGA prototyping solutions are now emerging to relieve design teams of the PCB development burden, potentially sparing them significant cost, development time and project risk over time. Whether to develop a prototype board in house or to use an off-the-shelf board, though, is an important decision that requires careful consideration of an organization’s verification needs, available resources, resident expertise, cost constraints and risk tolerance.

Verification Performance Is Key

Verification is one job that is never finished – it’s simply impossible to test a design for all cases, under all conditions it will face in its field application. The eternal pursuit of a more efficient and thorough methodology continues, and most are finding that traditional methods, like simulation, formal verification, and static timing analysis, need to be complemented with higher-performing solutions.

Regardless of the size or content of an ASIC design task, verification is a journey with multiple steps, one of which is invariably software simulation. Simulation, while used universally in early design stages and for block level validation, is just too slow to be practical for full-chip, at-speed verification. Even with the aid of an accelerator, it would take months, if not years, to verify a complete chip using a simulator. In addition, simulation cannot be relied upon to detect bugs that occur sporadically, that require real-world stimulus or that are not covered by a test bench. So, validating a design prior to tape-out, in a way that minimizes the risk of re-spin, calls for a higher performance verification method downstream.

Figure 1: Already today, more than 90 percent of all ASICs and ASSPs are either partially or completely prototyped in FPGAs, making FPGAs a pivotal IC verification methodology.

One higher-performance verification method employed by a number of companies is emulation. Despite the multi-million dollar price tag that is a barrier for most, there are advantages to this approach. Emulation, being a closed system, is typically fairly easy to use, essentially allowing the user to plug a design in and let it run with virtually no manual intervention. Highly sophisticated analysis and debugging software also make emulation a very comprehensive verification alternative.

Most design teams today using emulators, complement them with hardware-based prototyping as the final hand-off point for several reasons. Software content is increasingly prominent in ASICs and SOCs, and the multiple emulator seats required for software development are cost prohibitive. Another factor is that, while emulation system performance is significantly higher than software simulation, it is still at least an order of magnitude lower than hardware-based prototyping, limiting the extent of testing that can be performed in a given time frame. Finally, since external interfaces, such as USB ports, Ethernet ports, graphics and peripheral interfaces, tend to run faster than an emulator, speed bridges are needed to facilitate interaction with an emulation system.

So simulation, and emulation for those that use it, are valuable elements of a verification flow, but the performance and cost benefits of FPGA-based prototyping make it a superior solution for comprehensive, full-system, at-speed debugging and validation. A prototype, in most cases, runs fast enough that it can directly interface with and directly stimulate an external interface, using real-world stimulus. And, an attractive price point makes it feasible to provide multiple copies for software design teams, and its very high performance enables highly comprehensive testing within a typical verification time budget.

An ASIC Prototype Is Just A Board With A Bunch Of FPGAs On It – Right?

Since FPGA-based prototyping first emerged as a verification option, design teams have typically developed their own prototyping boards in-house. Though the board development effort absorbed some design resources, the relatively manageable size and complexity of prototype systems, combined with design productivity of FPGA and board-level design tools, helped minimize the development effort.

Perceived low variable cost is another reason that design teams have retained in-house control of board development. From a material cost perspective, for a single project, in-house board development can appear an inexpensive proposition. For example, a prototype that calls for four FPGAs at $4000 each and a $2000 PC board would require a total outlay of only $18,000 for materials.

The landscape for prototype board development is quickly changing. Unprecedented design complexity, combined with the availability of high capacity 90- and 65nm FPGAs, are driving the need for much more sophisticated boards. Today, prototype board development involves such design challenges as managing over 20 board layers, thousands of connections per FPGA, and other issues not the typical province of ASIC designers. Board development is becoming a task that not only demands unique expertise, but that also is taking longer to execute and introducing more risk into the system design process.

To Make Or To Buy

With the availability of off-the-shelf prototyping systems today, IC design managers who previously factored prototype board development into their project plans, or those who are introducing hardware-based verification into their flow for the first time, are well-advised to give due diligence to the make/buy decision. Some key factors to consider when assessing whether to make or buy are PCB design expertise, cost, ease of implementation, and risk.

Significant, specialized PCB design expertise is required to develop today’s prototype boards, with their 24-26 layers, high-pin-count FGPAs on board, thousands of signals to be routed, impedance matching, high speed traces, etc. Two design challenges that help illustrate the complexity of the design tasks to be managed are FPGA pin breakout pattern and connectivity between high pin count FPGAs.

Figure 2: Breakout Pattern

Breakout pattern refers to the way signals are physically routed away from an IC on a PCB. Devices with low-pin density, or for which signals can be routed with relative ease, do not present a design challenge. However, today’s 2”x2” FPGAs with about 2000 contact “bumps”, spaced ½ millimeter apart, are another matter. With a space of only about .2 mm between pins, it’s physically impossible to run traces or wires between them, or even to manage the connections with a few board layers. To maximize the signals accessed from the FGPA, 24-26 board layers are often required, as are complicated inter-layer connections such as blind and buried vias. Layout of boards of this complexity is very difficult and time-consuming, as is manufacturing.

What novice board designers tend to do when confronted with a complex breakout challenge is compromise on the number of signals utilized per FPGA, perhaps use 500 out of a possible 2000. This results in the use of more FPGAs than necessary, inflating the cost of the board. Even worse, the resulting prototype runs slower because there are insufficient signals to connect one FPGA to another and then to another.

Connectivity between FPGAs: The typical prototype board houses multiple FPGAs. As predicted by Rent’s Rule, though, the number of connections between FGPAs increases exponentially with functional partitioning. It’s impossible to have tens of thousands of direct connections between the FPGAs on a prototype board, so board design techniques are needed to manage the connections. One traditional technique is time division multiplexing (TDM), which results in multiple signals being conveyed across a single connection. However, TDM slows overall system performance and therefore needs to be applied in an intelligent way, requiring sophisticated partitioning software.

Other solutions employ a combination of board hardware and design automation, such that connections are managed while performance and design implementation flexibility are retained. In hardware, configurable physical connectors can be employed at the interface to each FPGA on board. In many instances, it is likely that these direct connections will be sufficient without the need for multiplexing. In the cases where a direct connection is not possible, design software can be employed to re-partition functionality in such a way that connections are achieved more optimally.
As board design becomes increasingly complicated, it will require higher levels of expertise beyond those of the traditional ASIC design team. In-house developed boards are more likely to be more prone to problems and to fall short of performance expectations, whereas, ready-made systems afford the benefit of having been designed and manufactured by experts. If an ASIC design team is to undertake PCB development and do so effectively, it must establish the resident PCB design expertise to address the mounting challenges associated with the task.

Technical issues aside, cost is certainly a consideration as well. Off-the-shelf systems might at first appear more expensive than their in-house counterparts. The cost discrepancy is however easily offset by savings in development resources and future reuse. Designing, contracting to build, and testing a board are non-trivial tasks that can absorb significant and costly development resources. The real cost of these resources, particularly given that board development can stretch into months, is non-negligible.

Another factor that can significantly impact the true cost of a prototyping system for an organization is reusability. Homegrown boards, while cheaper initially, are typically only used for a single design project. By contrast, off-the-shelf prototype systems are adaptable for subsequent projects, meaning a single board can be reused for two, three, four or more design projects. To the extent that a given team or organization has a continual stream of design projects, an off-the-shelf board offers the potential for significant cost savings and return on investment over time.

Since the ultimate goal of an IC design effort is the chip, not a prototyping board, ease of implementing the design in the hardware is another important factor to consider. To be certain, there is an advantage to having the prototyping hardware platform tied in to design tools. The closer the tie between tools and the prototype board, the faster and less error-prone the process and the better the prototype result. Of course, organizations developing their own boards, or preferring to use different design tools than prescribed by a third-party board provider can do so. It merely places more burden on the design team to synthesize and partition the design into the board implementation, then to verify its correct functionality.

How much risk a design team can assume must also be considered. Prototyping systems are used for very expensive, time-critical ASIC projects. Millions, or in some cases billions of dollars in revenue or market opportunity can be riding on getting a project out on time. Off-the-shelf boards from reputable providers with a tie in to design tools provide the lowest risk prototyping solution. Risk with a homegrown approach on the other hand, can be significant. Not only is there risk of a board design error, but it may even be difficult and time consuming to diagnose the source of the problem.

FPGA-Based ASIC Prototyping Is Growing Up!

Gone are the days when an ASIC design team can quickly turn out a prototype board. High performance board design considerations, such as managing IC breakout patterns, partitioning functionality between multiple FPGAs, and optimizing connections between FPGAs on the board are now highly critical to the realization of a working and high performance prototype.

Figure 3: The Confirma ASIC/ASSP Platform Flow

Off-the shelf prototyping systems, such as Synplicity’s Confirma™ ASIC/ASSP Verification Platform, have come to the rescue to relieve design teams of this development burden and allow them to focus on their core competencies. Such prototyping platforms developed by PCB and FPGA design experts and delivered by EDA providers such as Synplicity, improve verification quality, speed design cycles, offer long term cost savings, and allow organizations to apply resources to value-added activities.

Using FPGAs for ASIC prototyping helps designers to verify hardware, firmware and application software functionality before committing to first silicon. And prototyping helps companies to be successful and meeting tight product schedules without compromising on product features or product quality. However, there is plenty of room for improvement and the EDA vendors are challenged to live up to customer’s requirements and delivering a ‘grown up’ verification platform, not just a collection of point tools. The ultimate goal is to create an environment where designers can be productive quickly, debug rapidly, implement changes, and validate them without delay. Prototyping will be an indispensable part of every chip design and is already taking its place alongside the other, more traditional, verification methodologies, complementing and enhancing them. For many ASIC, ASSP and SoC designs, prototyping is already a “must-have” and very quickly it will be a mandatory step in each and every chip design project.

To learn more about the Confirma ASIC/ASSP Verification Platform, visit http://www.synplicity.com/products/prototyping_solutions.html.