Accelerating ASIC Verification Through FPGA Prototyping

The SOC Designer's Dilemma

Due to escalating costs associated with mask production, engineering, and design verification, developing ASICs at 0.13-µm geometries or below has topped $25 million. ASIC and ASSP designers today are increasingly under pressure to beat their competition to market while minimizing costs and maximizing productivity. The additional cost to respin the design—even without considering the lost market opportunity in an increasingly competitive market—can be crippling for most digital logic projects. To be successful, designers must balance fast time-to-market versus the time needed for verification prior to tapeout.

One of the biggest challenges for ASIC design is the length of the verification process. System designers cannot integrate and debug the hardware and software until the ASIC has been fabricated.

ASIC development teams need a design methodology that allows hardware and software co-design and co-verification to improve productivity, accelerate verification and enable quicker time-to-market. Figure 1 compares the time required for system development with and without hardware/software co-design.

Figure 1. System Development Timeline

Prototyping With FPGAs

With the increased capacity and performance of today’s FPGAs, ASIC prototyping using an FPGA has been widely adopted for the verification cycle. FPGAs can verify hardware, firmware and application software design functionality before first silicon is brought in-house. Prototyping can also relieve the time bottleneck and remove the high-caliber compute resources required to functionally verify medium and large designs. System performance is orders of magnitude faster than register transfer level (RTL) simulation, and the reliance on accurate intellectual property (IP) models is removed because the design runs in actual hardware. Hardware/software architectural tradeoffs can be evaluated in hardware rather than at high levels of abstraction, allowing designers to move design blocks to software for lower gate counts and power consumption or to hardware for increased performance.

Prototyping requires the ASIC design (or block being tested) to fit into the smallest number of FPGAs so that it can run at or near system speeds. Today’s FPGAs make ideal prototyping vehicles, offering the following capabilities:

• High logic capacity—FPGAs can fit more than 2 million ASIC gates. More than 50 percent of ASICs or ASSPs designed today can fit into a single FPGA.
• High performance— FPGAs can run at speeds up to 450 MHz, meeting real-time testing requirements.
• Flexible I/Os with high bandwidth— FPGAs support memory interfaces such as DDR2 and QDRAM. FPGAs also support high-speed LVDS and serializer/deserializer (SERDES) to optimize chip-to-chip communication, simplifying board interconnects for ASIC designs requiring multiple FPGAs.
• Flexible on-chip memory blocks—FPGAs have flexible embedded RAM blocks that can be configured for a wide range of applications such as on-chip cache and video frame buffers.
• Design security—FPGAs include encryption features to protect IP when the prototype is used in the field during market testing and customer beta programs.

ASIC Prototyping Design Flow

FPGA-based prototyping requires a design methodology that maps an ASIC design to one or more FPGAs and provides design visibility for debugging. An effective ASIC prototyping design flow addresses these considerations:

• Design partitioning—Larger ASIC designs must be partitioned into multiple FPGAs. Partitioning a design can be difficult unless the design was created with partitioning in mind, or the designer is experienced in partitioning.
• Design integrity between ASIC and FPGA implementations—While design and verification teams ideally would use the same design source files, constraints, and test benches for both implementations, ASIC and FPGA vendors have different design styles that optimize each architecture. Designers may have to make design tradeoffs to maintain design integrity between the two implementations.
• Design debugging—The goal of prototyping is to accelerate the design cycle by finding functional errors more quickly. Designers may need to view the states of internal FPGA signals and relate the results back to the source code.

Altera^® and Synplicity^® have developed a prototyping solution that addresses the partitioning, design optimization and debugging challenges designers face when prototyping ASICs with FPGAs (see Figure 2). This development flow uses Altera’s Quartus^® II and Synplicity’s Certify^® and Identify^® software to facilitate the design process, allowing designers to use the same source files, constraints and test benches for both the FPGA prototype and the ASIC.

Figure 2. Design Flow for FPGA-Based Prototyping

The Altera and Synplicity design flow also provides incremental compilation and automation through scripting to simplify the ASIC prototyping process. Incremental compilation using Quartus II software and the Synplicity MultiPoint™ technology helps designers achieve timing closure by reducing the compile times of synthesis and place and route and the number of iterations for each tool. The scripting support allows ASIC designers to automate their flow, similar to their ASIC design flow.

Design Partitioning
Synplicity’s Certify software automatically partitions ASIC designs into multiple FPGAs. Both fully automatic and a combination of automatic and manual register transfer level (RTL) partitioning are available. Certify software also offers I/O pin multiplexing technology that allows pin sharing, preventing the common problem of running out of I/O pins.

Design Optimization
Certify software optimizes timing paths for performance even when these paths cross multiple FPGAs. It also recognizes and translates ASIC design elements such as gate-level ASIC components and gated clock-tree structures into FPGA primitives. While these elements can be very difficult and time-consuming to edit manually, Certify software automatically converts them, improving productivity.

Design Debugging
Identify software provides different mechanisms for debugging, including probes, multiplexed probes and RTL support for Altera’s SignalTap® feature. Altera and Synplicity also provide the following on-chip debug solutions:

• SignalTap II logic analyzer—Captures and displays hardware events, delivers fast turn-around times, incrementally creates trigger conditions and adds signals to views, and uses captured data stored in on-chip RAM and JTAG interface for communication
• External logic analyzer interface—Allows external logic to view internal signals and dynamically switches internal signals to output
• Synplify Identify—Used for RTL source debugging and viewing waveforms

Conclusion

With today’s advances in FPGA performance, capacity and software tool support, prototyping with FPGAs is becoming a standard part of the verification process. Altera and Synplicity provide a streamlined design flow that addresses the ASIC verification challenges and enables the reduction of the verification timeline.