Using Synplify Pro/Premier Synthesis and Identify Debugging for Xilinx EDK designs

Introduction
Developing embedded systems on FPGAs is becoming increasingly popular with improving support for synthesizable and hard processor cores from different vendors.

As a parallel and equally important development, quality of embedded development tools from various FPGA vendors is continuously improving. This is enabling systems designers to develop large and fast embedded systems rapidly.

Why Synplify?

As any complex designs on FPGAs, embedded designs too are developed under tight timing, area, and runtime constraints. A good quality synthesis tool such as Synplify Pro or Synplify Premier not only delivers better performance and reliability as compared to other synthesis tools, but also helps a great deal in visualizing and debugging of designs, which is extremely important for rapid implementation of designs of embedded scale.

Xilinx EDK-ISE Flow

A complex embedded system is often made up of two distinct pieces of hardware: an EDK generated processor system, and custom logic designed by the user. These two are typically integrated in a top level file. An EDK user designs a processor system using an EDK GUI and exports it to the ISE (Project Navigator) environment for top level assembly and implementation. The diagram below shows a Xilinx EDK-ISE flow:

Xilinx EDK-Synplify Flow

An EDK user designs a processor system using EDK GUI and imports it into the Synplify Pro/Premier tool (GUI/Non-GUI) environment for top level assembly and implementation. The diagram below shows the Xilinx EDK-Synplify flow:

Getting performance with Synplify Pro/Premier/Certify

Embedded systems are often designed to fit into low power FPGAs (using less area) and are required to run the clock as fast as possible to deliver usable throughput. The cost factor adds up to use the lowest possible speed grade without compromising on system speed or area. These constraints often test the limit of a synthesis tool and at times require innovative measures to meet performance goals.

The Synplify Pro tool often performs better than any other FPGA synthesis tool and delivers better timing, lesser area and quicker runtime. As embedded designs are growing in size, doing full chip top-down synthesis with the Synplify Pro software as opposed to block level bottom-up synthesis in an EDK-ISE flow is going to significantly enhance the performance of a system.

The Synplify Premier tool enhances timing performance by doing physical synthesis. The Synplify Premier Design Planner is a perfect tool to perform system level floor planning and then run Physical synthesis on top of it.

When an embedded system is too large to fit into one single FPGA device, using the Certify tool can make the partitioning of a system into multiple chips extremely easy.

Visualizing an embedded system with HDL Analyst

While debugging a complex system, a user often ends up tracing various connections between RTL and an implementation netlist. This is a very tedious process if done through text files. The Synplify HDL Analyst with its RTL, Technology, and Physical graphical views and crossprobing abilities makes this process much simpler and efficient.

Debugging an embedded system with Identify

Embedded systems add another dimension to the complexity of a hardware system and hence require even more sophisticated debugging than simple hardware systems. As most of the processor bus signals are internal to the FPGA chip, using an external Signal Analyzer is often very difficult. The Identify tool helps a user tap internal signals on user-defined triggers and store their values into FPGA memories (block or distributed). The signal waveforms can then be downloaded into a software waveform viewer for independent analysis or comparison with software debugger data. The Identify tool also allows setting up of breakpoints and watchpoints in the RTL source code, which significantly enhances traditional software debugging commonly used in embedded systems.

Conclusion

Synplicity’s Synplify Pro and Synplify Premier tools, when used for synthesis of complex embedded systems, delivers the extra performance often needed on FPGAs platforms. Synplicity’s Certify design partitioning tool is well suited for embedded systems that need to be partitioned and implemented on multiple FPGA chips. Synplicity’s Identify hardware debugging tool enhances the embedded system debugging experience by allowing waveform viewing for system signals/busses internal to the FPGA and adding RTL breakpoints and watchpoints.

For more information on using Synplicity tools with Xilinx Embedded Development Kit, contact Synplicity at support@synplicity.com.