The following is an excerpt from a recently published white paper. Click the link at the bottom of the excerpt to register and read the entire paper.

FPGA Design Verification: Techniques for Creating a Fully Functional Design

Verifying designs for FPGA implementation requires a set of tasks and tools unique to the technology. Unlike designs destined for an ASIC, standard cell or custom implementation of an FPGA design does not generally have extensive resources allocated and preparation devoted to design verification. In many cases verification is more of an afterthought due to the ability to reprogram the device.

In reality the failure to plan and budget for FPGA design verification can cause product development disruptions and delays that are just as serious as those caused by masked technology re-spins. Assuming that verification risk is low, because errors can be corrected by reprogramming, fails to consider the effort required to track and correct the errors especially in complex, multiple-clock FPGA designs. The effect may be magnified considering the interdependence of device, system, and software development for example, any delay by the hardware team can hamstring the efforts of others.

There exists a hierarchy of verification techniques and tools available for use during the course of FPGA development that can greatly reduce the risks of using the devices. Within the hierarchy the initial verification steps tend to be performed at a high level to detect gross functional errors. As the verification process proceeds through to the ultimate goal of a fully functional design operating at speed, the design problems become increasingly esoteric. Often the problems are data or timing dependant. Some problems may be so rare as to require hours or even days of run time at full speed before a single occurrence can be detected. Such errors tend to be highly dependant on obscure events. When they do happen, the test environment must be prepared to capture them and provide data that will allow for analysis.

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