The Syndicated

Tips & Hints

Synplify Premier and Synplify Pro Software

Q. Can you integrate the Synplify Premier or Synplify Pro flow with an Altera’s SOPC Builder project?

A. Yes. Altera Embedded Development Tool (SOPC Builder) is used for designing embedded processor systems and subsystems in Altera FPGAs with embedded NIOS soft processor cores.

SOPC Builder System Generator writes out the HDL hardware platform in a specific format. Each hardware component is written out as an HDL file (or several HDL files) in the project directory. The Quartus project file (QPF) along with the Quartus settings file (QSF) is written out to run top level synthesis. The Quartus setup script (<system>_setup_quartus.tcl) is written out to load the project file along with pin location constraints (if any) into Quartus. Quartus runs synthesis and P&R on the top level in order to generate a top level hardware bitmap file

From a usability standpoint, a SOPC Builder-Synplify flow is not very different from the SOPC Builder-Quartus flow. SOPC Builder generates the hardware system in HDL format along with Quartus files, as described in the previous paragraph. At the end of this step the system is imported into Synplify using a utility called sopc2syn, and then synthesized and implemented as a regular hardware design.

The sopc2syn utility reads the SOPC Builder project file (PTF) and script file (SCR) to extract required information in order to construct a Synplify project file. The resultant project (*.prj) file can then be opened in the Synplify Pro or Synplify Premier tool. Synthesis is run with the push of ‘Run’ button to produce a bitmap file. This bitmap can then be imported back into the Quartus environment.

Here are the steps for running Synplify on an SOPC Builder design/system

1. Generate a system using SOPC Builder System Generator

Create the SOPC Builder system using the SOPC Builder GUI and generate all the files including PTF file by selecting “Generate”.

2. Import the SOPC Builder project into the Synplify Pro/Premier software

Open a command shell and type: sopc2syn –ptf <PTF file>

Example: sopc2syn -ptf E:/SOPC Builder/basic1/system.ptf

For more details on options, see command line help by typing: sopc2syn –help

3. Run Synplify Pro or Synplify Premier Synthesis

Open the synplify.prj file using the Synplify Pro or Synplify Premier software and click the “Run” button to synthesize the embedded hardware system. Make sure P&R is disabled as that is more conveniently done through Quartus GUI at this point.

4. Run Quartus P&R and download the programming file

This process requires an Altera FPGA Board. Here are the steps for this process:

Run Quartus P&R:

1. In Quartus, select File -> Open Project -> and browse to Synplify PAR Directory (par_1) and select the .qpf file as synplify/rev_1/par_1/small_eval_board.qpf

2. Compile the project by selecting Processing -> Start Compilation

3. If you have a Nios II license, a programming file (.sof) should be generated in the par_1 directory

Download the programming file:

1. Open Quartus Programmer through the icon or select Tools -> Programmer

2. Click on the “Add File” button in the Programmer pane and browse to synplify/rev_1/par_1/ for a programming file (.sof file).

3. Check Program/Configure check box in the GUI where file details are shown

4. Click on the “Start” button and you are done with the hardware portion

Synplify Premier Software

Q. Does the Synplify Premier tool allow modification to the Graph-based Physical Synthesis global placement options?

A. Yes. Starting with version 8.8.0, the Synplify Premier tool provides the capability to modify the Graph-based Physical Synthesis initial global placement options.

1. Begin by making a copy of the default options, located at <install>\lib\xilinx\xilinx_gp.opt, to another directory location and rename the file.

2. Modify the copied options file to incorporate the new settings.

3. Once the new options file is ready, set the environment variable “SYN_XILINX_GLOBAL_PLACE_OPT” to the location of the new options file, including the file name.

Synplify Premier will use the new options file during initial global placement.

Identify Software

Q. Can you build a complex state machine trigger In the Identify software?

A. Yes. Identify has a feature called “State Machine triggering” which allows you to create a state machine with a counter out of a sequence of trigger conditions, creating a very effective trigger.

You can set up the state machine trigger during instrumentation and program it dynamically during debug to create a complex, design-specific trigger.

You need to specify the number of Trigger States, Trigger Conditions (can be set dynamically in the debugger), and Counter width. A common design configuration is to trigger when a sequence of events occur, data collection is stopped and the sample data is downloaded by the corresponding debugger executable from the FPGA.

Specifying The Number Of Trigger States

You need to enable the statemachine triggering and specifying the states and triggering conditions through the Identify Instrumenter UI.

1. In the Identify Instrumentor UI, click on the “Actions” tab and select Configure IICE.

2. In the Configure IICE tab, select IICE Controller and then specify the number of Trigger States, Trigger Conditions, and Counter width.

Defining Trigger Conditions

Once the Instrumented design is synthesized, placed and routed, and programmed, you open the Identify Debugger UI and define the triggering conditions. If you right click on an instrumented signal in the Debugger, you will notice the following screen which enables you to define various triggering conditions.

Building The State Machine Trigger

Next you can build the state machine trigger from the Identify Debugger prompt.

Example:
statemachine addtrans -from 0 -to 1 -cond c0 -cntval 7 -trigger
statemachine addtrans -from 1 -to 0 -cond "cntnull"
statemachine addtrans -from 1 -to -1 -cnten –trigger

Once the state machine trigger is created, you can use the “statemachine info –all” command to get the state machine transitions and write the commands manually. You can the use the Identify Debugger UI to program the state machine trigger.