FPGA-based Prototyping Comes of Age - Full Visibility Technology Revolutionizes ASIC Verification

By Mario Larouche, Engineering Director, Synplicity, Inc.

As ASIC designers are well aware, verifying an ASIC becomes dramatically more difficult as chip complexity increases. Many have discovered, sometimes with devastating consequences, that verification capabilities lag behind the demands of the circuits they are supposed to validate. With Moore’s Law continuing its relentless progression, a tough situation is made even worse for those struggling with verification challenges.

Traditional verification techniques such as ASIC prototyping, simulation and emulation remain useful but are insufficient when applied to modern circuits – as an example, an assertion that requires only 3 seconds of real-time circuit activity to be tested can require up to 30 days at the kilohertz speed of a simulator. Advancements such as on-board logic analyzers are an improvement, but can still be lacking in important respects. FPGA-based prototyping delivers a cost-effective verification alternative, but has fallen short of providing full signal visibility.  While legacy methods are still useful, new capabilities have to be developed that cover the complexity of hardware/software systems being designed today. 

It is with FPGA-based prototyping, however, that technological advances hold the most promise. Unlike other methods such as simulation and emulation, FPGA-based prototyping can deliver an ASIC implementation capable of interacting with system software and providing at or near real-time transaction speeds.  What it has lacked is signal and state visibility; a more solvable problem than making simulation or emulation faster.  While some visibility enhancement technologies have been introduced to increase visibility in FPGA-based prototypes, they have fallen short of providing the full visibility required for debugging complex systems. 

Full visibility technology, deployed in an FPGA-based prototyping flow, holds the most promise for revolutionary improvement in ASIC and system verification. Having full signal visibility as a design runs at speed, and in the target system, is as close to verifying an actual production ASIC as possible without the time or high cost of a fab run. This type of technology can significantly speed debugging by capturing all design states prior to and after an event.  In addition, it allows the developer to debug in a familiar simulation environment where he is typically most comfortable and efficient. Coupling high-speed, low-cost FPGA hardware with emulation-quality debugging visibility and coverage can enable a clearly superior verification solution for ASIC designers

The Mounting Verification Crisis

Design engineers have for years referred to ASIC verification’s lag behind semiconductor IC capabilities as “the verification crisis.” Today’s system complexities take this crisis to new heights.  With each new silicon generation, more pre-silicon logic bugs occur in a design, driving the need to dedicate more engineers to the verification task and to invest more capital into verification tools.  This is further complicated by the need for system-level visibility, where hardware/software interactions can be observed.  Detecting system-level bugs and defects becomes a monumental task in deep submicron design, and failing to detect and correct these defects can be highly deleterious, sometimes leading to product recalls.

Traditional verification methods reveal strengths and weaknesses when confronted with today’s challenges (figure 1).  Classic “ASIC prototyping” affords system visibility, but because manufacturing an ASIC takes six to nine months and can cost $1M per trial in the deep submicron realm, custom silicon long ago ceased to be a viable mechanism for flushing out bugs.  As custom silicon becomes less of an option for ASIC verification, RTL simulation has become the mainstay of ASIC verification, providing a familiar, cheap, and early-in-the-design-flow verification.  That said, simulation of a complex ASIC can take significant time, and the test bench development effort can be monumental.  Furthermore, many designers forego testing out critical time-dependent assertions in simulation because it takes too long at the kilohertz speed of an RTL simulation environment.  Hardware/software co-verification also presents a test bench development challenge, and affords only a slight improvement in runtime.  C-level simulation makes it possible to forego test bench development because the actual system level stimulus is used, but it still takes significant time and lacks full signal visibility.  Recently, on-board logic analyzers have been employed to help improve visibility.  While an improvement, they still do not provide visibility into the complex interactions in real life situations.

Figure 1: Performance of Traditional ASIC Verification Methods

Emulation and traditional FPGA-based prototyping afford significant speed improvement over the other options, though there are still trade-offs.  Unlike simulation and co-verification options, emulation does provide full signal visibility, in significantly less time.  Emulators can be prohibitively costly, though, and, with execution speed in the 1MHz range, is still too slow for most designers.

Affording the best throughput time and near-system-level speed is FPGA-based prototyping.  In addition, FPGA-based prototyping makes it possible to apply real-time stimulus, and to thus achieve a true in-system test.  Historically, however, the FPGA-based approach has provided only limited visibility because not all signals were observable through the pins dedicated to testing.

Full Visibility Technology

Designers need a means to rapidly and thoroughly identify and eliminate design bugs prior to committing a project to silicon.  Specifically, they need the ability to identify and repair flaws at the point in the design flow at which they are introduced – typically the RTL.  Verification time must be minimized, though not at the expense of coverage.  And, especially critical for validation of today’s circuits is that verification be performed at or very near system speeds, and that it provides full signal visibility.    

These needs translate into demanding requirements for today’s verification tools and methodologies. A breakthrough in the technology itself is necessary.  TotalRecall™ Technology, developed by Synplicity, is such a breakthrough technology.  Using a combination of novel circuit design and synthesis techniques, the technology builds upon the cost, speed and productivity advantages of FPGA-based prototyping to enable true, full-signal visibility.  In doing so, debugging visibility that meets or exceeds that of emulation while executing 10 to 100 times faster can be achieved. 

This approach is unique in that it enables the designer to capture full signal and state information well before a problem event occurs. With TotalRecall technology the user captures the state of all registers, including memory, in his design for a specified number of clock cycles before a problem occurs. These design states, along with a testbench, are then exported to a standard HDL simulator where the user can restart simulation right before the problem occurs and replay the sequence as many times as necessary until the error is resolved. This technology is especially valuable for elusive errors such as sporadically occurring bugs, bugs precipitated by very specific hardware/software interactions or errors that require a significant number of clock cycles to occur.

The ability to test fixes within the simulation environment using the precise signal values that led to an error is also a unique approach. Other capture mechanisms typically use a circular buffer to hold information that precipitated an error, but the information retained is of a limited time period and represents a limited range of signal values. Instead, this enhanced approach works without a circular buffer, and enables users to see all signal activity within the number of cycles they specify leading up to an event. This spares them the effort of reselecting signals and recompiling, avoids the need to create a test bench and the inherent risk that the test bench will fail to create the correct sequence, and it allows them to work within a familiar simulation environment.

Another key distinction of this approach is that it enables assertions to be fully tested at the RTL.  The ability to synthesize assertions into hardware during synthesis, and then exercising those assertions on real hardware, allows designers to fully assess device behavior over a series of cycles – something that is virtually impossible using a traditional RTL simulation approach. 

Because the TotalRecall Technology can be completely automated a design flow that employs the technology differs very little from a standard ASIC flow (figure 2).  The developer needs only to specify, or mark, into which module (or all modules) in their RTL code he desires total visibility.  Debugging trigger points, assertions and watch points can also be specified as in a standard flow.  The design is then synthesized into an FPGA or multiple FPGAs, allowing it to be run in the ASIC as a functional equivalent to the ASIC.  When a trigger point is reached during operation, mechanisms within the FPGA logic recreate all signal values within that entire module for the specified number of prior clock cycles.  The designer then works within his familiar simulation environment to debug and repair errors.

Figure 2: Sample RTL Design Flow with Total Visibility Technology

A Breakthrough

FPGA-based prototyping with full visibility represents an innovation in ASIC functional verification that is revolutionary compared to other alternatives (figure 3).  It has been recognized as a breakthrough in verification technology in that it gives the designer the ability to use low-cost hardware to achieve full signal visibility using real-time stimulus.   It also enables the designer to identify bugs, even sporadic bugs or assertion failures that evade detection by other methods.  Other solutions may use real stimulus and real circuit values, but none can as quickly and accurately recreate the conditions that precipitated an error.  Because of its unique capabilities, TotalRecall Technology makes assertion-based verification at the RT level feasible for the first time.  Though designers have long known the value of assertion-based verification, and have even been using assertions in synthesis, not until now have they had the capability to fully exercise and test out assertions at the RT level. 

Figure 3: Signal Visibility of ASIC Verification Methods

FPGA-based prototyping has been used for years to verify ASICs, and prototyping methodologies are well supported by FPGA vendors and board suppliers. Now, with full signal visibility, this verification methodology is positioned to quell the verification crisis and become a preferred means for designers to functionally verify their ASICs.