The following is an excerpt from a recently published white paper. Click the link at the bottom of the excerpt to register and read the entire paper.

Efficient Development of Wireless IP with High Level Modeling and Synthesis

Over the last decade, digital wireless technologies have become one of the leading drivers of semiconductor growth and also a source of increasing design complexity. In nearly every application category, new wireless standards are pushing for higher performance and capacity by using more sophisticated algorithms. A good example is 802.11n, the much anticipated new WLAN technology that promises to deliver data rates up to 600Mbps. Other examples include WiMAX, 3G and 4G Cellular technologies, Digital Video Broadcast (DVB), Software Defined Radio for military radios, and so on. Most of the end markets driving these applications are either in early stages of very rapid growth, or are more established markets under pressure to upgrade performance and capacity to meet competitive demands. In either case, the demands trickle down to the design teams who are challenged to deliver the increasingly complex IP in less time.

In the past, the semiconductor industry has met this type of challenge by introducing higher levels of design abstraction. The most recent example is the growth of Verilog and VHDL methodology over the last 15 years for logic design. IC engineers can rapidly model, simulate, and synthesize implementation at the logic level which realizes a huge productivity improvement over design at the gate or transistor level.

The same automation and productivity gains can be applied at the DSP and wirelesss algorithm level by providing an abstraction layer to RTL implementation. This abstraction will intrinsically be quite different, however, because DSP is dominated by digital arithmetic and specialized signal analysis techniques. A good high level abstraction layer for DSP should shield the designer from implementation details of the mathematical operations like multipliers and adders. Of more significance is automating the architectural optimization techniques that are so common for practical arithmetic datapath realization. This includes pipelining for performance, and resource sharing expensive operators like multipliers for area and multi-channel efficiency. These are very common and important optimizations, and a good DSP abstraction layer should automate them and save the designer the time and effort of implementing them by hand.

The Synplify® DSP software from Synplicity achieves this goal by giving designers a technology independent, high-level DSP modeling environment and a synthesis engine that automatically creates optimized DSP arithmetic into silicon.

With a comprehensive DSP library, excellent fixed-point analysis tools, multi-rate capability, and hardware abstraction, algorithms are easier to describe and verify. By providing constraint driven architectural synthesis, design-space exploration is enabled, achieving more optimal results and full device and technology portability.

To read the entire white paper, click here to register.