Synplicity and Xilinx Create Design Task Force to Tackle Timing Closure for Ultra High-Capacity FPGAs

On May 15, 2006 Synplicity and Xilinx announced the formation of a joint Ultra High-Capacity Timing Closure Task Force. The task force consists of engineering teams from both companies who will collaborate to develop next-generation design automation solutions enabling system designers to take full advantage of the capacity and performance of ultra high-density 65-nanometer (nm) designs.

The Ultra High-Capacity Task Force will initially focus on providing dramatic improvements in overall quality of results and run time, and ensuring the stability of results when small changes are made to designs. Ultimately, the goal of the Task Force is to allow designers to realize the benefits of near push-button results for ultra high density designs along with the ability to complete multiple design iterations per day.

The industry’s first 65-nm Virtex™-5 FPGA family, introduced by Xilinx on May 15, 2006, includes devices with up to 330,000 logic cells, 10-Mb on-chip memory, 1,200 I/Os and a host of additional hardened intellectual property (IP) blocks. Future platforms will add even greater density points and capabilities further expanding the reach of advanced FPGA architectures across a wide range of application domains. Because of the wide variety of applications enabled by these ultra high-capacity devices, the Task Force will focus on delivering multiple design flows and tools optimized to meet the unique goals of these types of designs.

“We’re very pleased to take the existing strong relationship between our two companies to the next level,” said Bruce Talley, vice president, Design Software Division at Xilinx. “The Synplicity team has a great deal of experience and track record of innovation when it comes to high performance, complex FPGA design with products like Synplify Pro and Synplify Premier physical synthesis. This joint task force provides an opportunity to more quickly leverage engineering expertise and creativity across our development organizations.”

“Xilinx is breaking new ground with its 65-nm Virtex-5 FPGA product line,” said Ken McElvain, CTO at Synplicity. “These platforms require tools that are optimized to solve timing closure issues that arise from the unprecedented levels of performance and capabilities. The creation of this task force is targeted at helping our mutual customers deploy the Virtex-5 ultra-high capacity devices in their systems in the fastest, most efficient manner.”

The joint Task Force expects the first of these tools and methodologies to be available in the first half of 2007.