Q3, 2007
High Speed Printed Circuit Boards For ASIC Prototyping
Reconfiguration for Reliability Tools
Efficient DSP Algorithm Development For FPGA And ASIC Technologies
Tips & Hints
Certify Software
Q. Can you perform a generated clock conversion in the Certify tool?
A. Yes. The Certify software performs a generated clock conversion when the Fix Generated Clocks option in the Implementation Options dialog box is enabled. The generated clock logic is replaced during synthesis with logic that uses the initial clock with an enable.
With generated-clock optimization, the original circuit functionality is preserved while performance is improved by reducing clock skew.
The fix generated clocks option has the following values:
Value |
Effect |
0
|
Does not report any generated clock conversions. |
1 |
Only reports sequential elements that could not be converted. |
2 |
Reports the conversion status of all sequential elements. |
3 |
Disables the option. This is the default. |
To perform generated-clock optimization, the following conditions must be met:
1. The combinational logic must be driven by flip-flops.
2. The input flip-flops cannot have an active set or reset.
3. All input flip-flops must be driven by the same edge of the same clock.
4. With generated-clock optimization, you do not have to specify a primary clock.
NOTE: If a user partitions the generated clock logic and destination flip-flops in different FPGA’s, then the generated clock conversion will not occur across FPGA boundaries. The user will need to replicate the logic.
Synplify Premier Software
Q. Can you disable tunneling of instances in a region in the Synplify Premier Design Planner tool?
A. Yes. To avoid tunneling into instances that are not assigned to a region (instances that are mapped inside a region which was not assigned to it), you can assign the region as an ‘IP Block’.
To assign a region as an IP Block, right-click on the region in the Design Planner window. Choose ‘Region Type’, then select ‘IP Block’.
The following illustration indicates that region rgn1 is an IP Block region. The RTL view instance U0 is assigned to rgn1.
Synplify Premier Software
Q. Should translated NDF cores be included in the Synplify Premier project if the corresponding NGC core is already included?
A. No.The recommended Synplify Premier flow for Xilinx generated core IPs is to include only EDN and NGC cores. Adding a translated NDF file to a project containing the original NGC is tantamount to adding the same core twice. Synplify Premier translates NGC cores to NDF cores as part of the automated flow. Additionally, having both NGC cores and the corresponding translated NDF cores can potentially lead to uniquification issues during place-and-route. Only EDN and NGC cores should be added to the Synplify Premier project.
