The Syndicated

Incrementally Achieve Faster Compile Times in High-Density FPGAs

By Phil Simpson and Ajay Jagtiani, Altera Corporation

Introduction

Over the last eight years, FPGAs have experienced a 30X increase in logic density and memory bits. In contrast, CPU speed has only increased by a factor of 11X during the same period. With FPGA capacity outpacing CPU speed, FPGA designers require design tools and methodologies that speed compile times and allow them to iteratively and efficiently debug, add features and close timing. This article will present solutions based on incremental design to increase productivity for engineers who are designing with high-end FPGAs such as the Altera® Stratix II and Stratix III FPGAs.

Leveraging Computer Technology

While CPU speeds have not kept pace with the increasing FPGA density, computer architectures have evolved so they can provide a performance boost. Multiple-core CPUs are now becoming conventional for computer workstations. New generations of processors support two processors on a single chip, and motherboards support two or more processors on a single board. Leveraging the multiple CPUs to improve productivity is both a function of tool support and of design methodology. Tools that make design partitioning easy and, ideally, directly support multiprocessor architectures can help designers improve productivity, but a design methodology must complement this approach.

Incremental Design Methodology

The use of an incremental compilation design methodology together with parallel processing on compute farms provides the biggest impact in reducing the compile time. In conventional FPGA design, a hierarchical design is flattened into a single netlist before logic synthesis and fitting, requiring the entire design to be recompiled every time the design changes. Incremental compilation allows designers to partition a design along any of its hierarchical boundaries. These design blocks, or partitions, can be individually synthesized and fit, then merged at the top-level. This methodology preserves performance on optimized partitions and a significant reduction in the overall compile time.

Built-in support for incrementation compilation exists in many tools today, including Altera’s Quartus® II and Synplicity’s Synplify Pro software. This feature enables designers to partition their designs based on logical hierarchies using either a top-down or bottom-up design methodology. In a top-down flow, designers can design each partition serially, saving the results and recompiling only the partitions that have changed, reducing design compile time.

To further reduce compile times, designers can use a combination of a top-down design flow with a bottom-up design methodology. The designer first partitions the FPGA design based on the logical hierarchy. Each partition can be assigned to a different engineer, who creates the register transfer level (RTL) design and completes functional closure for the assigned partition. In many design teams, a single designer is responsible for the integration of the whole design.

Designers can specify timing constraints between partitions and locations constraints for the partitions at the top-level of the design. In some cases, partitioning can be automated, for example, by using the Generate Bottom-Up Design Partitions Scripts option in the Quartus II software to create individual scripts for each partition containing the timing constraints and wrapper file for the partition and location constraints for each partition. In other cases, the user must create time budgets for each partition, which then can be incorporated into an overall top-down run for the design, or for incremental design runs.

If the designer needs to make a late engineering change, only the partition that is changed needs to be recompiled and then merged with the top-level netlist. This process preserves the fit and performance of the other partitions in the design. This solution also provides a fast debug solution for designs that use embedded logic analyzers. After any design changes, only the changed partitions are recompiled rather than the entire design. This flow not only results in a shorter overall compile time, but improves time-to-market because the designer can quickly debug the design while preserving the performance of the unchanged parts of the design.

A summary of this flow is shown in Figure 1 (below).

Conclusion

An incremental compilation design methodology combined with efficient use of computer resources enables users to greatly reduce FPGA compile times and speed time-to-market. This is achieved by partitioning a design so they can be processed by multiple workstations, reducing synthesis time. Synplify Pro synthesis is a key part of this design flow, and can be used to target the latest devices, such as Stratix III FPGAs. This design methodology targeting high-capacity FPGAs, combined with support for multiprocessor computers, provides the fastest FPGA compile times in the industry.