The following is an excerpt from a recently published white paper. Click the link at the bottom of the excerpt to register and read the entire paper.

Verifying Complex ASICs through FPGA-based Prototyping

By Ashok Kulkarni, Sr. Technical Marketing Manager, Synplicity, Inc.

Introduction – Verification Challenges of Complex ASICs and SoC

The relentless pace in the advancement of process technology, now at 65 nanometers, has made it feasible to implement highly complex designs with several million gates that operate in the GHz frequency range. This pace has been both a blessing and a challenge. With higher gate counts, it is now possible to have designs that encompass an entire system on a chip or SoC or other complex ASICs. The challenge today is validating the intended functionality and timing prior to committing the design to silicon. What makes the verification process a daunting task is the large number of test vectors required to completely verify the design. Due to short product life cycles and a limited window of market opportunity, re-spinning a faulty ASIC/SoC is not an option. In addition, the mask cost alone can exceed a million dollars and even more when considering the added engineering costs.

While there are distinct differences between ASIC and SoC devices, the need to create a prototype prior to tape-out still remains. The most distinguishing capabilities are the need to run large amounts of software content on the SoC and the ability to quickly create derivative products from the original design. These requirements mandate that the software engineers have access to the prototyping system to run diagnostics, firmware, and the application software prior to the availability of silicon.

This paper examines how prototyping using advanced RTL partitioning and RTL debugging tools helps you achieve predictable results with lower costs. Specifically, you can achieve high target speed and, at the same time, create multiple boards (replicates) at reduced costs to enable project engineers to simultaneously accomplish system integration and early software development. The flow described in this paper is fully compatible with many of the off-the-shelf prototyping boards available from any number of board vendors. Furthermore, the design flow can easily be upgraded by using the latest FPGA technology the moment it becomes available.

Various verification strategies have been used and each has its own pros and cons. This paper discusses the following topics: verification strategies, the benefits of prototyping over emulation, various technical issues to consider prior to prototyping, the prototyping flow using Synplicity’s Certify® product, and a debug methodology using Synplicity’s Identify® product.

To read the entire white paper, click here to register.